In recent years, the number of quadrature amplitude modulation (QAM) channels used for narrowcast digital television services has increased substantially. Most multiple system operators (MSOs) are providing more and more unicast QAM channels to support growth brought on by the success of video on demand (VOD) services. This has been driven, in large part, by an increase in offerings of high definition television services and content. Deployment of switched digital video (SDV) in order to provide an increased number of multicast content offerings is driving QAM channels even further. Additional QAM channels are also being deployed for MSOs cable modem termination system (CMTS) equipment.
While the number of QAM channels is growing, MSOs are reducing the size of the service groups they offer to make more efficient use of their cable television networks. Smaller service groups result in improved service quality. Moreover, reusing spectrum available in a network is advantageous in that it supports narrowcast service growth.
As a result of the above evolution in the CATV marketplace, more dense edge QAMs are required to reduce the cost of the equipment and the resulting environmental requirements in headends and distribution hubs. In order to help meet this need, a new equipment architecture option has been developed that enables the implementation of denser network architectures in a modular headend structure. Together with this, a new class of equipment is under development which is known as Converged Multiservice Access Platform (CMAP). CMAP implements the functions of the CMTS and edge QAM for all narrowcast and broadcast digital services. An introduction to CMAP can be found in the article Comcast Update: What is a CMAP, J. Salinger and J. Leddy, Comcast Corporation, Feb. 1, 2010.
In order to implement a CMAP system, it is necessary to provide a suitable modulator to add digital television data to a carrier waveform using QAM. The prior art contains various different architectures for accomplishing this, but they all have drawbacks. Some known solutions utilize an older, less efficient method in terms of multiply operations per channel or operations per sample. Such methods are best described by FIGS. 1 and 2. FIG. 1 is a sub-block diagram of the signal processing chain for a single channel in a first prior art modulator architecture. FIG. 2 illustrates how this single channel architecture is replicated in parallel and summed in order to implement an entire downstream spectrum.
As illustrated in FIG. 1, the modulator includes a symbol mapper 10, the output of which is provided to a first Square Root Raised Cosine Filter (SRRC) and interpolator 12 and a second SRRC and interpolator 14. The outputs of SRRC and interpolators 12 and 14 are provided to additional respective interpolators 16 and 20 which raise the output frequency of the signals to a range that is compatible with the sample rate of the downstream digital to analog converter (DAC) 28. The output of interpolator 16 is modulated with the sine function output from a digital quadrature oscillator 18 using mixer 22. The output of interpolator 20 is modulated with the cosine function output from the oscillator 18 using mixer 24. The outputs from the mixers 22, 24 are summed in adder 26, and the result is provided to a digital to analog converter (DAC) 28 in a conventional manner.
FIG. 2 is a prior art example of the parallelization of single channel sub-blocks. This apparatus, generally designated 30, replicates the single channel architecture of FIG. 1 in parallel and sums the results. The output from the DAC represents the entire downstream spectrum.
It is known (see, e.g., Harris, et al “Digital Receivers and Transmitters Using Polyphase Filter Banks for Wireless Communications,” IEEE Transactions on Microwave Theory and Techniques, Vol. 51, No. 4, April 2003) that the type of architecture illustrated in FIGS. 1 and 2 is much less efficient than other known architectures, such as a Fast Fourier Transform (FFT) based Polyphase Channelizer approach. A Polyphase Channelizer is illustrated in FIG. 3, and has been demonstrated to be much more efficient (in terms of multiply operations per channel output sample).
As shown in FIG. 3, a plurality of channel streams 32a . . . 32n are input to a 720 point Inverse Discrete Fourier Transform (IDFT) processor 34. The output of processor 34 is resampled by a polyphase resampling filter 36 and then processed by a commutator 38 to produce output to be converted to analog by a digital-to-analog converter (DAC). The functions of the polyphase resampling filter 36 are to resample the channels to 6 MHz centers, provide matched filtering, and to provide channelization filtering. Such an implementation has several limitations for a modular CMAP (M-CMAP) system, which include:                1. For the number of filter taps per phase specified in FIG. 3, it can not meet the specifications for Adjacent Channel, Wideband Noise, and Carrier Suppression. To meet these specifications would require more than doubling the number of filter taps per phase and prohibit an efficient, cost effective solution.        2. It can not meet the 5 ppm frequency accuracy specifications.        3. It can only modulate a single mode (256 or 64 QAM) across all channels, whereas the CMAP specification requires mixed mode (simultaneous 64 and 256 QAM) operation across all channels. Specifically, if there are N total channels, the specification requires M channels of 64 QAM and K channels of 256 QAM, where K+M=N.        4. The Polyphase Resampler requires 720×47 REAL multipliers, which overly constrains the resources and layout for any potential FPGA implementation.        5. Only the STD frequency plan is provided using this design, whereas the HRC frequency plan is also required for M-CMAP        
It would be advantageous to provide an M-CMAP implementation in which these limitations are overcome. More particularly, it would be advantageous to provide a DSP implementation of a full spectrum DOCSIS/CATV downstream modulator that uses a single FPGA or ASIC and a single D/A converter. Still further, it would be advantageous for such an implementation to make use of the FFT based polyphase channelizer approach and which implements an IDFT by utilizing a DCT (Direct Cosine Transform) and DST (Direct Sine Transform) computation that is highly efficient and is computed based on an N/4 sized FFT kernel, wherein after the DCT/DST, the signal is converted from complex to real in order to both utilize a single DAC and exploit the corresponding reduction in complexity.
The present invention provides methods and apparatus having the aforementioned and other advantages. Moreover, the unique combination of components/techniques disclosed herein provides various improvements over previously known structures and techniques.